verilog compiler error: near ";": syntax error, unexpected ';' -
i'm trying write traffic light fsm code green, yellow, red has delay of 20 time units. goes green-yellow-red-yellow- green. code , i'm getting error while using 'repeat' delay.
errors:
error: c:/users/desktop/design/tlights.v(33): near ";": syntax error, unexpected ';'
error: c:/users/desktop/design/tlights.v(37): near ";": syntax error, unexpected ';'
error: c:/users/desktop/design/tlights.v(44): near ";": syntax error, unexpected ';'
`define delay 20; module tlights(clk, rst, y); input clk, rst; output [1:0]y; reg [1:0]y; reg [1:0] cs,ns; integer p; parameter red = 2'd2; parameter orange = 2'd1; parameter green = 2'd0; parameter s0 = 2'd0; parameter s1 = 2'd1; parameter s2 = 2'd2; always@(posedge clk or negedge rst) begin if(!rst) begin cs<=s0; end else cs<=ns; end always@(cs) begin case(cs) s0: begin repeat (`delay) @(posedge clk); // <-- error here ns=s1; end s1: begin repeat (`delay) @(posedge clk); // <-- error here if (p==0) ns =s2; else ns=s0; end s2: begin repeat (`delay) @(posedge clk); // <-- error here ns<=s1; end default: ns<=s0; endcase end always@ (cs) begin case(cs) s0:begin y<=2'b00; p<=0; end s1:y<=2'b01; s2:begin y<=2'b10; p<=1; end endcase end endmodule
the problem `define statement. `define similar #define in c/c++. statements literal substitution , terminator end of line, not semi-colon. repeat (`delay) means repeat ( 20; ). remove ; , simulate.
even with correction not synthesize. blocking statements (i.e. @,#, , wait) not allowed inside combinational logic. synthesizable, you'll need add flip-flops counter. next state , next counter combinational logic should following:
always @* begin // default value ns = cs; next_counter = counter + 1; // update value case(cs) s0: begin if (counter >= `delay) begin ns = s1; next_counter = 0; end end /* ... */ endcase end also, remember assign flops non-blocking (<=). blocking (=) assigning combinational logic.
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